CGS delay development board: Difference between revisions

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There is a development area to the right end of the board, allowing a 74HC4046 and associated components to be fitted, including two 4024 divider chips. The theory is that voltage control of the delay can be achieved using the 74HC4046, and frequency dependent delays achieved using the phase-locked-loop. At this point this area has not been developed, and is up the individual experimenter to use or ignore as s/he sees fit.
 
{| class="wikitable"
=== Connections to and from the PCB ===
|+ style="text-align:left"|Numbered/coded components
;B IN
|-
:Buffer in. The input to the op-amp buffer.
! Component!!style="text-align:left"|Function
;BIOUT
|-
:Buffer inverted output.
| RA6||Pull-down resistor to be added if A6 line is cut.
;B OUT
|-
:Buffer output.
| RA7||Pull-down resistor to be added if A7 line is cut. There is no provision for resistor on the write line, so one would need to be added on the rear of the PCB.
;C IN
|-
:Compressor input. Feed input signal in here.
| Rfb||Value not specified in the app. note. Feedback resistor. Try something between 10k and 100k. There are two Rfb resistors.
;C OUT
|-
:Compressor output. Feed this to the input of the delay
| RG||Gain setting resistor for the buffer. 47k would give a gain of 1, 4k7 would give a gain of 10, etc.
;D IN
|}
:Delay input.
;D OUT
:Delay output.
;E IN
:Expander input. Feed from the output of the delay
;E OUT
:Expander output. Feed this to the buffer, if needed, or to your output jack via an external 1k resistor.
;FB IN
:Feedback input.
;FB OUT
:Feedback output. Basically a SPST switch is wired between these two connections to enable the repeat function. A variable resistor may give some degree of control to reduction of successive echoes. As it stands, a standard level control "potentiometer" will not work. (i.e. use two wires to the pot, not three. Earthing one end of the pot's travel will foul things up.)
;+5
:Connect to 5 volt power supply.
;+15
:Connect to 15 volt power supply.
;-15
:Connect to negative 15 volt power supply.
;AGND
:Analog ground. Connect to 0V at PSU if possible, or to 0 volt bus if not.
;DGND
:Digital ground. Connect to 0V at PSU if possible, or leave disconnected if not. There is a 10R resistor linking the two grounds on the PCB.
;A6
:Pair of pads. Provision to cut the trace and route the A7 address line through a switch for reducing the minimum delay. (untested)
;A7
:Pair of pads. Provision to cut the trace and route the A6 address line through a switch for reducing the minimum delay. (untested)
;W
:Pair of pads. Provision to cut the trace and route the Write line through a switch to allow for "holding" of a captured sample. (untested)
;Reset
:Not used. May be needed if experimenting.
;SEL
:Select between 64k or 256k modes if using 41256 RAM chip, or permanently wire to DGND if using 4164
;SHORT
:Sets short delay mode. Tie the other two length selectors to DGND. Connect this pin to +5 volts.
;MED
:Sets medium delay mode. Tie the other two length selectors to DGND. Connect this pin to +5 volts.
;LONG
:Sets long delay mode. Tie the other two length selectors to DGND. Connect this pin to +5 volts.
 
{| class="wikitable"
=== Numbered/coded components===
|+ style="text-align:left"|Connections to and from the PCB
;RA6
|-
:Pull-down resistor to be added if A6 line is cut.
! Pad ID!!style="text-align:left"|Function
;RA7
|-
:Pull-down resistor to be added if A7 line is cut.
| B IN||Buffer in. The input to the op-amp buffer.
:There is no provision for resistor on the write line, so one would need to be added on the rear of the PCB.
|-
;Rfb
| BIOUT||Buffer inverted output.
:Value not specified in the app. note. Feedback resistor. Try something between 10k and 100k. There are two Rfb resistors.
|-
;RG
| B OUT||Buffer output.
:Gain setting resistor for the buffer. 47k would give a gain of 1, 4k7 would give a gain of 10, etc.
|-
 
| C IN||Compressor input. Feed input signal in here.
There are some capacitors marked as high precision in the app. note, and on the circuit diagram above. I suggest using 5% mylar capacitors or better (styrene, poly prop, poly carb, 1%, 2%, etc.) in these positions. Match them if you have a capacitance meter.
|-
| C OUT||Compressor output. Feed this to the input of the delay
|-
| D IN||Delay input.
|-
| D OUT||Delay output.
|-
| E IN||Expander input. Feed from the output of the delay
|-
| E OUT||Expander output. Feed this to the buffer, if needed, or to your output jack via an external 1k resistor.
|-
| FB IN||Feedback input.
|-
| FB OUT||Feedback output. Basically a SPST switch is wired between these two connections to enable the repeat function. A variable resistor may give some degree of control to reduction of successive echoes. As it stands, a standard level control "potentiometer" will not work. (i.e. use two wires to the pot, not three. Earthing one end of the pot's travel will foul things up.)
|-
| +5||Connect to 5 volt power supply.
|-
| +15||Connect to 15 volt power supply.
|-
| -15||Connect to negative 15 volt power supply.
|-
| AGND||Analog ground. Connect to 0V at PSU if possible, or to 0 volt bus if not.
|-
| DGND||Digital ground. Connect to 0V at PSU if possible, or leave disconnected if not. There is a 10R resistor linking the two grounds on the PCB.
|-
| A6||Pair of pads. Provision to cut the trace and route the A7 address line through a switch for reducing the minimum delay. (untested)
|-
| A7||Pair of pads. Provision to cut the trace and route the A6 address line through a switch for reducing the minimum delay. (untested)
|-
| W||Pair of pads. Provision to cut the trace and route the Write line through a switch to allow for "holding" of a captured sample. (untested)
|-
| Reset||Not used. May be needed if experimenting.
|-
| SEL||Select between 64k or 256k modes if using 41256 RAM chip, or permanently wire to DGND if using 4164
|-
| SHORT||Sets short delay mode. Tie the other two length selectors to DGND. Connect this pin to +5 volts.
|-
| MED||Sets medium delay mode. Tie the other two length selectors to DGND. Connect this pin to +5 volts.
|-
| LONG||Sets long delay mode. Tie the other two length selectors to DGND. Connect this pin to +5 volts.
|}
 
Before you start assembly, check the board for etching faults. Look for any shorts between tracks, or open circuits due to over etching. Take this opportunity to sand the edges of the board if needed, removing any splinters or rough edges.
Line 103 ⟶ 108:
 
=== Notes ===
* There are some capacitors marked as high precision in the app. note, and on the circuit diagram above. I suggest using 5% mylar capacitors or better (styrene, poly prop, poly carb, 1%, 2%, etc.) in these positions. Match them if you have a capacitance meter.
* PCB is 6" x 2" with 3mm mounting holes 0.15" in from the edges.
 
== CC-BY-NC ==
Readers are permitted to construct these circuits for their own personal use only. Ken Stone retains all rights to his work.
 
== See also ==
Line 110 ⟶ 119:
 
== References ==
* ''[https://web.archive.org/web/20180209234737fw_20180209234737f/http://www.cgs.synth.net:80/modules/cgs44_ddb.html Delay Development Board]'' (archived) by Ken Stone, 2001, with permission of the author - archived
 
== External links ==
Line 118 ⟶ 127:
* The delay chip can be purchased from [https://web.archive.org/web/20180403145124/http://smallbearelec.com/ Small Bear Electronics].
 
[[Category:CGS modularsignal processors]]