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[[File:cgs_photo_cgs36_pulse_divider.jpg|center|600px]]
'''CGS36''' the '''CGS pulse divider and booleanBoolean logic''' consists of several parts, a pulse divider with integer divisions between 2 and 8, and several logic elements. The divider is used to generate interrelated pulses for use in creating poly-rhythms, and unusual sequences. It can also be run at audio frequencies as a sub-oscillator/sub harmonic generator. The output pulse from each division is one clock cycle in length, and the relationship between pulses is fixed. Specifically, the /4 output will correspond to every second pulse from the /2 output. Likewise, the /8 will correspond to every second pulse from the /4 output, and the /6 will correspond to every second pulse from the /3 output. Needless to say, the /2 and /3 groups are not related to each other, or to the /5 or /7 outputs. All however share a common external reset, so they can be synchronized. All outputs go high on reset.
 
As well as the pulse divider, there are also four booleanBoolean logic elements. Two are basic inverters. If you apply a LOW (e.g. a gate output in its OFF state) they will give a HIGH (gate ON) output, and vice versa. The OR gate has two inputs, and gives a HIGH whenever one or both inputs are HIGH. The AND gate has two inputs, and gives a HIGH only when both inputs are HIGH. Both of these have built in LED monitors. Unlike the Analog Logic module, these are strictly for processing gate, trigger and clock signals.
 
* This module will work on +/-12 volts. See the textparts list for resistor value changes.▼
== Some ideas on how to use this module ==▼
 
▲== Some ideas on how to use this module ==
Feed a clock signal into the input of the pulse divider. The divided signal is available simultaneously for each output. If running at audio frequencies, feed some of these to a mixer or other signal processing device. If running at low speed, try driving two different sequencers at the same time from different divisions.
 
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[[File:cgs_schem_cgs36_boolean_r1-1.gif|thumb|center|800px|Rev 1.2 Logic, (revision 1.1 is at [[:File:cgs_schem_cgs36_boolean.gif]])]]
The booleanBoolean logic are simple discrete R/DTL designs. When either input of the OR gate receives a voltage high enough, the first transistor is switched on, pulling the base of the second transistor low, and thus turning it on as well. This results in the output being pulled up to the voltage governed by the resistor divider. In the case of the AND gate, both input transistors must be turned on before the output transistor can be turned on, as the input transistors are in series with each other. The inverters are basically just the same as the first stage of the OR gate, with the exception of there being only one input.
 
== Construction ==
[[File:cgs_pcb_cgs36v13cgs_pcb_cgs36_pulse_divider.gif|thumb|center|600px|The component overlay. ClickRev through for an enlarged printable version1.1.]]
[[File:cgs_pcb_cgs36v13.gif|thumb|center|600px|The component overlay Rev 1.3. Click through for an enlarged printable version.]]
Note: '''On the first run of the PCBs, the 820R and 680R in the AND gate were reversed.''' To get around this they were swapped in assembly. If not one output will be a little lower than the other. This isn't critical.
 
Note: '''On the first run of the REV1.2 PCBs, the boards were actually labelledlabeled REV1.1.''' They are identifiable because this revision mark is in the same box as the CGS36 ID. All Rev1.2 versions: the 1k5 in the second inverter should be 1k8.
 
VER1.3 PCBs have the upper part of the output dividers marked as RA on the PCB. These resistors are 1k8 for +/-15V operation and 1k5 for +/-12 volt operation. Likewise the two 1k8 resistors in the inverters should be 1k5 for 12 volt operation. The two 1k5 resistors in the OR and AND gates could probably be increased to 1k8 for 15 volt operation. Check your output voltages when you have assembled them. Ideally the voltages will swing between 0 volts and +5 volts. Some small variance either way is nothing to be concerned about.
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When inserting the IC in its socket, if used, take care not to accidentally bend any of the pins under the chip. Also, make sure the notch on the chip is aligned with the notch marked on the PCB overlay.
 
=== Notes ===▼
* On REV1.1 boards the output swing of the inverters are not limited like those in the other gates. Adding a resistor from the collector to emitter of the transistors (one per inverter) will reduce the "high" level output. I would suggest something in the range of 470R to 680R.▼
* Make sure you use a standard 4000 series CMOS, not 74XXX4000 series, e.g. CD4017, MC14017, HEF4017. Markings such as HC4017, HCT4017 imply 74HC4017 and 74HCT4017 and are unsuitable.▼
▲* This module will work on +/-12 volts. See the text for resistor value changes.
* A 10 to 22 ohm resistor can be used instead of the Ferrite beads. If you don't care about power-rail noise, just use a link instead.▼
* On some boards there is an unmarked capacitor near the power connector. This can be anything in the range of 10n to 100n, and ceramic, or it can be omitted altogether.▼
* PCB measures 6" x 2" with 3mm mounting holes 0.15" in from the edges.▼
 
== Parts list ==
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| cgs36 PCB||align=right|1
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▲=== Notes ===
▲* On REV1.1 boards the output swing of the inverters are not limited like those in the other gates. Adding a resistor from the collector to emitter of the transistors (one per inverter) will reduce the "high" level output. I would suggest something in the range of 470R to 680R.
▲* Make sure you use a standard 4000 series CMOS, not 74XXX4000 series, e.g. CD4017, MC14017, HEF4017. Markings such as HC4017, HCT4017 imply 74HC4017 and 74HCT4017 and are unsuitable.
▲* A 10 to 22 ohm resistor can be used instead of the Ferrite beads. If you don't care about power-rail noise, just use a link instead.
▲* On some boards there is an unmarked capacitor near the power connector. This can be anything in the range of 10n to 100n, and ceramic, or it can be omitted altogether.
▲* PCB measures 6" x 2" with 3mm mounting holes 0.15" in from the edges.
 
== CC-BY-NC ==
Readers are permitted to construct these circuits for their own personal use only. Ken Stone retains all rights to his work.
 
== See also ==
* [[CGS pulse divider and booleanBoolean logic]] for version 1.3.4
* [[CGS parts FAQ]]
* [[CatGirl_Synth#The_CGS_modules|The CGS modules]]
 
== References ==
* [https://web.archive.org/web/20161227161727fw_20161227161727f/http://www.cgs.synth.net:80/modules/cgs36v1_pulse_divider.html Pulse Divider and Boolean Logic for music synthesizers.] (archived) by Ken Stone, 2001, with permission of the author - archived
 
== External links ==
* [http://groups.yahoo.com/group/cgs_synth CGS Synth discussion group], for discussion of locating parts, modifications and corrections etc.
 
[[Category:CGS modularclock/gate/trigger processors]]
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