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[[File:cgs_photo_cgs36_pulse_divider.jpg|center|600px]]
'''CGS36''' the '''CGS pulse divider and booleanBoolean logic''' consists of several parts, a pulse divider with integer divisions between 2 and 8, and several logic elements. The divider is used to generate interrelated pulses for use in creating poly-rhythms, and unusual sequences. It can also be run at audio frequencies as a sub-oscillator/sub harmonic generator. The output pulse from each division is one clock cycle in length, and the relationship between pulses is fixed. Specifically, the /4 output will correspond to every second pulse from the /2 output. Likewise, the /8 will correspond to every second pulse from the /4 output, and the /6 will correspond to every second pulse from the /3 output. Needless to say, the /2 and /3 groups are not related to each other, or to the /5 or /7 outputs. All however share a common external reset, so they can be synchronized. All outputs go high on reset.
As well as the pulse divider, there are also four booleanBoolean logic elements. Two are basic inverters. If you apply a LOW (e.g. a gate output in its OFF state) they will give a HIGH (gate ON) output, and vice versa. The OR gate has two inputs, and gives a HIGH whenever one or both inputs are HIGH. The AND gate has two inputs, and gives a HIGH only when both inputs are HIGH. Both of these have built in LED monitors. Unlike the Analog Logic module, these are strictly for processing gate, trigger and clock signals.
This module will work on +/-12 volts. See the parts list for resistor value changes.
[[File:cgs_schem_cgs36_boolean_r1-1.gif|thumb|center|800px|Rev 1.2 Logic, (revision 1.1 is at [[:File:cgs_schem_cgs36_boolean.gif]])]]
The booleanBoolean logic are simple discrete R/DTL designs. When either input of the OR gate receives a voltage high enough, the first transistor is switched on, pulling the base of the second transistor low, and thus turning it on as well. This results in the output being pulled up to the voltage governed by the resistor divider. In the case of the AND gate, both input transistors must be turned on before the output transistor can be turned on, as the input transistors are in series with each other. The inverters are basically just the same as the first stage of the OR gate, with the exception of there being only one input.
== Construction ==
== See also ==
* [[CGS pulse divider and booleanBoolean logic]] for version 1.4
* [[CGS parts FAQ]]
* [[CatGirl_Synth#The_CGS_modules|The CGS modules]]
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