CGS pulse divider and Boolean logic: Difference between revisions

As well as the pulse divider, there are also five boolean logic elements. Two are basic inverters. If you apply a LOW (e.g. a gate output in its OFF state) they will give a HIGH (gate ON) output, and vice versa. The OR gate has two inputs, and gives a HIGH whenever ''one'' or ''both'' inputs are HIGH. The AND gate has two inputs, and gives a HIGH only when ''both'' inputs are HIGH. The fifth is an exclusive OR gate (XOR), giving a LOW when both inputs are within 1.2 volts of each other, and a HIGH when they are not. The OR, AND and XOR also offer inverted outputs, giving the option of using them as NOR, NAND and XNOR gates. Unlike the Analog Logic module, these are for processing gate, trigger and clock signals, although the XOR gate can accept linear inputs as well.

 

 

Feed a clock signal into the input of the pulse divider. The divided signal is available simultaneously for each output. If running at audio frequencies, feed some of these to a mixer or other signal processing device. If running at low speed, try driving two different sequencers at the same time from different divisions.

 

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* Make sure you use a standard 4000 series CMOS, not 74XXX4000 series, e.g. CD4017, MC14017, HEF4017. Markings such as HC4017, HCT4017 imply 74HC4017 and 74HCT4017 and are unsuitable. MC4017 is also unsuitable.

* PCB measures 6" x 2" with 3mm mounting holes 0.15" in from the edges.