CGS pulse divider and Boolean logic

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Cgs photo cgs36v14 pulse divider.jpg

CGS36 the CGS pulse divider Boolean logic module consists of several parts, a pulse divider with integer divisions between 2 and 8, and several logic elements. The divider is used to generate interrelated pulses for use in creating poly-rhythms, and unusual sequences. It can also be run at audio frequencies as a sub-oscillator/sub harmonic generator. The output pulse from each division is one clock cycle in length, and the relationship between pulses is fixed. Specifically, the /4 output will correspond to every second pulse from the /2 output. Likewise, the /8 will correspond to every second pulse from the /4 output, and the /6 will correspond to every second pulse from the /3 output. Needless to say, the /2 and /3 groups are not related to each other, or to the /5 or /7 outputs. All however share a common external reset, so they can be synchronized. All outputs go high on reset.

As well as the pulse divider, there are also five Boolean logic elements. Two are basic inverters. If you apply a LOW (e.g. a gate output in its OFF state) they will give a HIGH (gate ON) output, and vice versa. The OR gate has two inputs, and gives a HIGH whenever one or both inputs are HIGH. The AND gate has two inputs, and gives a HIGH only when both inputs are HIGH. The fifth is an exclusive OR gate (XOR), giving a LOW when both inputs are within 1.2 volts of each other, and a HIGH when they are not. The OR, AND and XOR also offer inverted outputs, giving the option of using them as NOR, NAND and XNOR gates. Unlike the Analog Logic module, these are for processing gate, trigger and clock signals, although the XOR gate can accept linear inputs as well.

This module will work on +/-12 volts. See the text for resistor value changes.

Some ideas on how to use this module

Feed a clock signal into the input of the pulse divider. The divided signal is available simultaneously for each output. If running at audio frequencies, feed some of these to a mixer or other signal processing device. If running at low speed, try driving two different sequencers at the same time from different divisions.

Try feeding the /8 output into the reset - this will force all to synchronize to a /7 count, with the lesser divisions becoming "syncopated".

The AND gate could be used to control a clock signal. If the second input is LOW, no clock signal passes. If the second input is high, the signal passes unimpeded. Of course, there are a lot more things that can be done with the logic gates. For example, the /6 and /7 outputs could be ANDed together, and that would give a pulse every 6 x 7 (42) clock pulses (i.e. 1 pulse immediately the pulse divider is reset, and the second 42 pulses after that etc.).

A little on how it works

Cgs schem cgs36v14 pulse divider.gif

The clock and reset signals are processed by the TL072. The reset is sensitive to rising edges only, meaning that a continuous gate signal would initially reset the dividers, then allow the module to continue counting. The Reset button on the other hand is wired so that holding it in will stop all counting, and hold all outputs high for as long as the button is held.

Following the input processor are four 4017 decade counters wired to give the various divisions. Where possible, sub-divisions have been taken from the same chip, with the various pulses being ORed together by diodes. Each output is buffered by an emitter follower. Many different types of small signal or switching transistors (e.g. BC547) can be used here without affecting the performance.

Cgs schem cgs36v14 boolean.gif

The Boolean logic are simple discrete R/DTL designs. When either input of the OR gate receives a voltage high enough, the first transistor is switched on, pulling the base of the second transistor low, and thus turning it on as well. This results in the output being pulled up to the voltage governed by the resistor divider. In the case of the AND gate, both input transistors must be turned on before the output transistor can be turned on, as the input transistors are in series with each other. The inverters are basically just the same as the first stage of the OR gate, with the exception of there being only one input.

See CGS54 the CGS XOR/XNOR logic module for a further explanation of how the Exclusive OR gate works.

Construction

The component overlay. Click through for an enlarged printable version.

VER1.4 PCBs have the upper part of the output dividers marked as RA, RB, RC, RD and RE on the PCB. These resistors are 1k8 for +/-15V operation and 1k5 for +/-12 volt operation. Check your output voltages when you have assembled them. Ideally the voltages will swing between 0 volts and +5 volts. Some small variance either way is nothing to be concerned about.

Before you start assembly, check the board for etching faults. Look for any shorts between tracks, or open circuits due to over etching. Take this opportunity to sand the edges of the board if needed, removing any splinters or rough edges.

When you are happy with the printed circuit board, construction can proceed as normal, starting with the resistors and other low profile components such as diodes first, followed by IC sockets if used, then moving onto the taller components.

At this point, if surface mount capacitors have been specified, turn the board over and add these now. It is not difficult to solder these onto the board with a regular soldering iron. First put a small amount of solder on one pad. Place the component between the two pads, one end resting on the solder you just put there. Press the component down with your finger nail or a small tool, and briefly reapply heat to the solder. The part will sink into it and remain held there. Solder the other end of the component to its pad. Re solder the first pad to make sure you have a good connection.

If you are unable to use the surface mount devices, you could use small ceramic monoblock capacitors instead, soldering them directly to the associated IC's power pins on the solder side of the PCB, or the appropriate pad in the case of transistors/capacitors.

Take particular care with the orientation of the polarized components such as electrolytics, diodes, IC and transistors.

When inserting ICs in their sockets, take care not to accidentally bend any of the pins under the chip. Also, make sure the notch on the chip is aligned with the notch marked on the PCB overlay.

Pad ID Function
0V 0V connection for all LED cathodes, jack sleeve connections etc.
+VE +VE to reset push button.
CLK Clock input
RSB Optional Reset button
RST Reset input
Lx LED anode for div by x
/x Divide by x output
II Inverter 1 input
IO Inverter 1 output
IL Inverter 1 LED anode
JI Inverter 2 input
JO Inverter 2 output
JL Inverter 2 LED anode
RL OR gate LED anode
RI OR gate input
RO OR gate output
RN Test point/not used
AL AND gate LED anode
AI AND gate input
AO AND gate output
AN Test point/not used
XI XOR/XNOR gate input
XO XOR gate output
XL XOR gate LED anode
NO XNOR gate output
NL XNOR gate LED anode

Parts list

This is a guide only. Parts needed will vary with individual constructor's needs.

Part Quantity
Capacitors
100n 1206 SMD/SMT 12
10n 1
10uF 25V 2
Resistors
1k 19
10k 10
15k 1
100k 23
4M7 2
RLED 10k (see text) 13
RA 1k8 (see text) 7
RB 1k8 (see text) 2
RC 1k8 (see text) 2
RD 1k8 (see text) 2
RE 1k8 (see text) 2
Semi's
LED 13
1N4148 29
TL072 1
CD4017 4
BC547 12
BC557 2
Misc.
Ferrite bead 2
0.156 4 pin connector 1
CGS36 VER1.4 PCB 1

Notes

  • Make sure you use a standard 4000 series CMOS, not 74XXX4000 series, e.g. CD4017, MC14017, HEF4017. Markings such as HC4017, HCT4017 imply 74HC4017 and 74HCT4017 and are unsuitable. MC4017 is also unsuitable.
  • PCB measures 6" x 2" with 3mm mounting holes 0.15" in from the edges.

CC-BY-NC

Readers are permitted to construct these circuits for their own personal use only. Ken Stone retains all rights to his work.

See also

References

External links

Suppliers