CGS pulse divider and Boolean logic (previous revisions): Difference between revisions
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== Construction == |
== Construction == |
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[[File: |
[[File:cgs_pcb_cgs36_pulse_divider.gif|thumb|center|600px|The component overlay Rev 1.1.]] |
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[[File:cgs_pcb_cgs36v13.gif|thumb|center|600px|The component overlay Rev 1.3. Click through for an enlarged printable version.]] |
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Note: '''On the first run of the PCBs, the 820R and 680R in the AND gate were reversed.''' To get around this they were swapped in assembly. If not one output will be a little lower than the other. This isn't critical. |
Note: '''On the first run of the PCBs, the 820R and 680R in the AND gate were reversed.''' To get around this they were swapped in assembly. If not one output will be a little lower than the other. This isn't critical. |
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